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r2061 series 3 wire interface real-time clock ics wi th battery backup switch-over function no.ea-112-070427 1 outline the r2061 is a cmos real-time clock ic connected to t he cpu by three signal lines, ce, sclk, and sio, and configured to perform serial transmission of time and calendar data to the cpu. further, battery backup switchover circuit and a voltage detector. the periodic interr upt circuit is configured to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. the 2 alarm interrupt circuits generate interrupt signals at preset times. as the oscillation circ uit is driven under constant voltage, fluctuation of the oscillator frequency due to supply voltage is small, and the time keeping current is small (typ. 0.4 a at 3v). the oscillation halt sensing circuit can be used to judge the valid ity of internal data in such events as power-on; the supply voltage monitoring circuit is configured to record a drop in supply voltage below two selectable supply voltage monitoring threshold settings. the oscillation adjus tment circuit is intended to adjust time counts with high precision by correcting deviations in the oscillat ion frequency of the quartz cr ystal unit. battery backup switchover function is the automatic switchover circuit between a main power supply and a backup battery of primary or secondary battery. switchover is execut ed by monitoring the voltage of a main power supply, therefore the voltage of a backup battery voltage is not relevant. since the package for these ics is ssop16 (5.0x6.4x1.25: r2061sxx) and ffp12 (2.0x2.0x1.0: r 2061kxx), high density mounting of ics on boards is possible. features ? minimum timekeeping supply voltage typ. 0.75v (max. 1.00v); vdd pin ? low power consumption typ. 0.4 a (max. 1.0 a) at v dd =3v ? built-in backup switchover circuit (can be used for a primary battery, a secondary battery, or an electric double layer capacitor) ? three signal lines (ce, sclk, and sio) r equired for connection to the cpu. ? (maximum clock frequency of 1mhz (with v cc = 3v) ) ? time counters (counting hours, minutes, and second s) and calendar counters (c ounting years, months, days, and weeks) (in bcd format) ? interrupt circuit configured to generate interrupt si gnals (with interrupts ranging from 0.5 seconds to 1 month) to the cpu and provided with an interrupt flag and an interrupt halt ? 2 alarm interrupt circuits (alarm_w for week, hour, and minute alarm settings and alarm_d for hour and minute alarm settings) ? built-in voltage detector with delay ? with power-on flag to prove that the power supply starts from 0v ? supply voltage monitoring circuit with two supply voltage monitoring threshold settings ? automatic identification of leap years up to the year 2099 ? selectable 12-hour and 24-hour mode settings ? built-in oscillation stabilizati on capacitors (cg and cd) ? high precision oscillation adjustment circuit ? cmos process ? package ssop16 (5.0mm x 6.4mm x 1.25mm : r2061sxx), ffp12 (2.0mm x 2.0mm x 1.0mm : r2061kxx
r2061 series 2 pin configuration vdcc sclk vcc nc nc 1 2 3 4 5 6 7 9 top view r2061sxx(ssop16) vsb 13 15 sio nc ce nc vdd int r 10 11 12 14 oscin cin 8 16 vss oscout vdd vcc sio vss 10 11 12 1 2 3 4 top view r2061kxx(ffp12) 7 vsb ce scl k vdcc cin 5 6 9 8 oscin oscout intr block diagram oscout vss vdd intr cpu power supply oscin vcc vsb cpu real time clock sclk ce c3 battery voltage monitor vdcc voltage detector sw1 sw2 sio c2 r1 level shifter delay cin voltage reference c1
r2061 series 3 selection guide in the r2061xxx series, output vo ltage and options can be designated. part number is designated as follows: r2061k01-e2 part number r2061abb -cc code description a designation of the package. k: ffp12 s: ssop16 bb serial number of voltage detector setting etc. cc designation of the taping type. only e2 is available. part number package -v det1 (switch-over threshold) dc electrical characteristics r2061k01-e2 ffp12 1.70(typ.) p. 6 r2061k03-e2 ffp12 2.80(typ.) p. 8 R2061S02-E2 ssop16 2.40(typ.) p. 7
r2061 series 4 pin description symbol item description ce chip enable input the ce pin is used for interfacing with the cpu. should be held high to allow access to the cpu. incorporat es a pull-down resistor. should be held low or open when the cpu is powered off. a llows a maximum input voltage of 5.5 volts regardless of supply voltage. sclk serial clock input the sclk pin is used to input cl ock pulses synchronizing the input and output of data to and from the sio pin. allows a maximum input voltage of 5.5 volts regardless of supply voltage. sio serial input / output the sio pin is used to input or output data intended for writing or reading in synchronization with the sclk pin. intr interrupt output the intr pin is used to output alarm interrupt (alarm_w) and alarm interrupt (alarm_d) and output periodic in terrupt signals to the cpu signals. disabled at power-on from 0v. nch. open drain output. vcc main battery input supply power to the ic. vsb power supply input for backup battery connect a primary battery for backup. normally, power is supplied from vcc to the ic. if vcc level is equal or less than ?v det1 , power is supplied from this pin. oscin oscout oscillation circuit input / output the oscin and oscout pins are used to connect the 32.768-khz quartz crystal unit (with all other oscillation ci rcuit components built into the r2061 series). vdd positive power supply input the vdd pin is connected to the power supply. connect a capacitor as much as 0.1 f between vdd and vss. in the case of using a secondary battery, connecting the secondary battery to this pin is possible. vdcc vcc power supply monitoring result output while monitoring vcc power supply, if the voltage is equal or lower than ?v det1 , this output level is ?l?. when vdcc becomes ?l?, sw1 turns off and sw2 turns on. as a result, power is supplied from vsb pin to the internal real time clock. when vcc is equal to +v det1 or more, sw1 turns on and sw2 turns off. after t delay passed, vdcc output becomes off, or ?h?. nch open-drain output. cin noise bypass pin to stabilize the internal reference, connect a capacitor as much as 0.1uf between this pin and vss. vss negative power sup supply input the vss pin is grounded.
r2061 series 5 absolute maximum ratings (v ss =0v) symbol item pin name description unit v cc supply voltage 1 vcc -0.3 to +6.5 v v dd supply voltage 2 vdd -0.3 to +6.5 v v sb supply voltage 3 vsb -0.3 to +6.5 v input voltage 1 ce, sclk -0.3 to +6.5 v input voltage 2 sio -0.3 to v cc +0.3 v v i input voltage 3 cin -0.3 to v dd +0.3 v output voltage 1 intr , vdcc -0.3 to +6.5 v v o output voltage 2 sio -0.3 to v cc +0.3 v i out maximum output current vdd 10 ma p d power dissipation topt = 25 c 300 mw topt operating temperature -40 to +85 c tstg storage temperature -55 to +125 c recommended operating conditions (v ss =0v, topt=-40 to +85 c) symbol item pin name min, typ. max. unit vaccess supply voltage vcc power supply voltage for interfacing with cpu -v det1 5.5 v v clk minimum timekeeping voltage cgout,cdout=0pf *2), *3) 0.75 1.00 v f xt oscillation frequency 32.768 khz v pup pull-up voltage intr , vdcc 5.5 v *1) -v det1 in vaccess specification is guaranteed by design. *2) cgout is connect ed between oscin and vss, cdout is connected between oscout and vss. r2061 series incorporates the capacitors between oscin and vss, between oscout and vss. then normally, cgout and cdout are not necessary. *3) quartz crystal unit: cl=6-8pf, r1=30k ?
r2061 series 6 dc electrical characteristics ? r2061k01 (unless otherwise specified: v ss =0v, v sb =3.0v, v cc =2.0v, 0.1uf between vdd and vss, cin and vss, topt=-40 to +85 c) symbol item pin name conditi ons min. typ. max. unit v ih1 ?h? input voltage 1 ce, sclk 0.8xv cc 5.5 v ih2 ?h? input voltage 2 sio 0.8xv cc v cc +0.3 v il ?l? input voltage ce, sio sclk -0.3 0.2xv cc v i oh ?h? output current sio v oh =v cc -0.5v -0.5 ma i ol1 ?l? output current 1 sio 0.5 i ol2 ?l? output current 2 intr v ol =0.4v 2.0 i ol3 ?l? output current 3 intr v dd ,v sb ,v cc =1.4v v ol =0.4v 0.2 ma i il input leakage current sclk v i =5.5v or v ss -1.0 1.0 a r dnce pull-down input register ce 40 120 400 k ? i oz1 output off-state current 1 sio v o =5.5v or v ss -1.0 1.0 a i oz2 output off-state current 2 intr , vdcc v o =5.5v or v ss -1.0 1.0 a i sb time keeping current at backup mode vsb v cc =0v, v sb =3.0v, v dd , output=open 0.4 1.0 a i sbl leakage current of backup pin at vcc_on vsb v cc =3.0v, v sb =5.5v or 0v, v dd , output=open -1.0 1.0 a v deth supply voltage monitoring voltage ?h? vsb topt=25 c 1.90 2.10 2.30 v v detl supply voltage monitoring voltage ?l? vdd topt=25 c 1.20 1.35 1.50 v -v det1 detector threshold voltage (falling edge of vcc) vcc topt=25 c 1.657 1.700 1.743 v +v det1 detector released voltage (rising edge of vcc) vcc topt=25 c 1.731 1.785 1.839 v ? v det ? topt detector threshold and released voltage temperature coefficient vcc, vsb topt=-40 to 85 c *1) 100 ppm / c v ddout1 vdd output voltage 1 vdd topt=25 c, v cc =2.0v, i out =0.5ma v cc - 0.12 v cc - 0.04 v v ddout2 vdd output voltage 2 vdd topt=25 c, v cc =1.4v, v sb =3.0v, i out =0.1ma v sb - 0.08 v sb - 0.02 v cg internal oscillation capacitance 1 oscin 10 cd internal oscillation capacitance 2 oscout 10 pf *1) guaranteed by design.
r2061 series 7 ? r2061s02 (unless otherwise specified: v ss =0v,v sb =v cc =3.0v, 0.1uf between vdd and vss, cin and vss, topt=-40 to +85 c) symbol item pin name condi tions min. typ. max. unit v ih1 ?h? input voltage 1 ce, sclk 0.8xv cc 5.5 v ih2 ?h? input voltage 2 sio 0.8xv cc v cc +0.3 v il ?l? input voltage ce, sclk sio -0.3 0.2xv cc v i oh ?h? output current sio v oh =v cc -0.5v -0.5 ma i ol1 ?l? output current 1 sio 0.5 i ol2 ?l? output current 2 intr v ol =0.4v 2.0 i ol3 ?l? output current 3 vdcc v dd ,v sb ,v cc =2.0v v ol =0.4v 0.5 ma i il input leakage current sclk v i =5.5v or v ss -1.0 1.0 a r dnce pull-down input register ce 40 120 400 k ? i oz1 output off-state current 1 sio v o =5.5v or v ss -1.0 1.0 a i oz2 output off-state current 2 intr , vdcc v o =5.5v or v ss -1.0 1.0 a i sb time keeping current at backup mode vsb v cc =0v, v sb =3.0v, v dd , output=open 0.4 1.0 a i sbl leakage current of backup pin at vcc_on vsb v cc =3.0v, v sb =5.5v or 0v, v dd , output=open -1.0 1.0 a v deth supply voltage monitoring voltage ?h? vsb topt=25 c 1.90 2.10 2.30 v v detl supply voltage monitoring voltage ?l? vdd topt=25 c 1.20 1.35 1.50 v -v det1 detector threshold voltage (falling edge of vcc) vcc topt=25 c 2.34 2.40 2.46 v +v det1 detector released voltage (rising edge of vcc) vcc topt=25 c 2.44 2.52 2.60 v ? v det ? topt detector threshold and released voltage temperature coefficient vcc, vsb topt=-40 to 85 c *1) 100 ppm / c v ddout1 vdd output voltage 1 vdd topt=25 c, v cc =3.0v, i out =1.0ma v cc - 0.12 v cc - 0.04 v v ddout2 vdd output voltage 2 vdd topt=25 c, v cc =2.0v, v sb =3.0v, i out =0.1ma v sb - 0.08 v sb - 0.02 v cg internal oscillation capacitance 1 oscin 10 cd internal oscillation capacitance 2 oscout 10 pf *1) guaranteed by design.
r2061 series 8 ? r2061k03 (unless otherwise specified: v ss =0v, v sb =3.0v, v cc =3.3v, 0.1uf between vdd and vss, cin and vss, topt=-40 to +85 c) symbol item pin name conditi ons min. typ. max. unit v ih1 ?h? input voltage 1 ce, sclk 0.8x v cc 5.5 v ih2 ?h? input voltage 2 sio 0.8x v cc v cc +0.3 v il ?l? input voltage ce, sclk sio -0.3 0.2xv cc v i oh ?h? output current sio v oh =v cc -0.5v -0.5 ma i ol1 ?l? output current 1 sio 0.5 i ol2 ?l? output current 2 intr v ol =0.4v 2.0 i ol3 ?l? output current 3 vdcc v dd ,v sb ,v cc =2.0v v ol =0.4v 0.5 ma i il input leakage current sclk v i =5.5v or v ss -1.0 1.0 a r dnce pull-down input register ce 40 120 400 k ? i oz1 output off-state current 1 sio v o =5.5v or vss -1.0 1.0 a i oz2 output off-state current 2 intr , vdcc v o =5.5v or v ss -1.0 1.0 a i sb time keeping current at backup mode vsb v cc =0v, v sb =3.0v, v dd , output=open 0.4 1.0 a i sbl leakage current of backup pin at vcc_on vsb v cc =3.3v, v sb =5.5v or 0v, v dd , output=open -1.0 1.0 a v deth supply voltage monitoring voltage ?h? vsb topt=25 c 1.90 2.10 2.30 v v detl supply voltage monitoring voltage ?l? vdd topt=25 c 1.20 1.35 1.50 v -v det1 detector threshold voltage (falling edge of vcc) vcc topt=25 c 2.73 2.80 2.87 v +v det1 detector released voltage (rising edge of vcc) vcc topt=25 c 2.85 2.94 3.03 v ? v det ? topt detector threshold and released voltage temperature coefficient vcc, vsb topt=-40 to 85 c *1) 100 ppm / c v ddout1 vdd output voltage 1 vdd topt=25 c, v cc =3.3v, i out =1.0ma v cc - 0.12 v cc - 0.04 v v ddout2 vdd output voltage 2 vdd topt=25 c, v cc =2.0v, v sb =3.0v, i out =0.1ma v sb - 0.08 v sb -0. 02 v cg internal oscillation capacitance 1 oscin 10 cd internal oscillation capacitance 2 oscout 10 pf *1) guaranteed by design.
r2061 series 9 ac electrical characteristics unless otherwise specified: v ss =0v,topt=-40 to +85 c input and output conditions: v ih =0.8 v cc ,v il =0.2 v cc ,v oh =0.8 v cc ,v ol =0.2 v cc ,cl=50pf v dd 1.7v *1) sym -bol item condi- tions min. typ. max. unit t ces ce set-up time 400 ns t ceh ce hold time 400 ns t cr ce recovery time 62 s f sclk sclk clock frequency 1.0 mhz t ckh sclk clock ?h? time 400 ns t ckl sclk clock ?l? time 400 ns t cks sclk set-up time 200 ns t rd data output delay time 300 ns t rz data output floating time 300 ns t cez data output delay time after falling of ce 300 ns t ds input data set-up time 200 ns t dh input data hold time 200 ns t delay output delay time of voltage detector time keeping 100 105 110 ms *1) vcc voltage interfacing with cp u is defined by vaccess (p.5 recommended operating conditions ) *) for reading/writing timing, see ?p.30 interfacing with the cpu ? considerations in reading and writing time data under special condition ?. sclk t ces sio(read cycle) sio(write cycle) ce t rd t ckl t cez t ds t dh t rd t ceh t ckh t cks t cr t rz vdcc vcc t delay +v det1
r2061 series 10 package dimensions ? r2061kxx 9 7 6 4 3 1 10 12 1pin index 2.0 0.1 0.2 0.15 0.35 2.0 0.1 2pin index 0.5 0.3 0.15 0.103 0.25 0.35 1.0max 0.27 0.15 (bottom view) 0.5 0.05 0.17 0.1 unit: mm
r2061 series 11 ? r2061sxx 16 9 1 m 8 4.4 0.2 6.4 0.3 0.5 0.3 0.225typ 0.65 0 to 10 0.1 0.1 0.10 0.15 0.22 0.15 +0.1 - 0 . 05 5.0 0.3 1.15 0.1 +0.1 - 0 . 05 unit: mm taping specification the r2061 series have one designated taping direction. t he product designation for the taping components is "r2061s/kxx-e2".
r2061 series 12 general description ? battery backup switchover function the r2061 series have two power supply input, or vcc and vsb. with monitoring vcc pin input voltage, which voltage between the two is supplied to the internal power supply is decided. refer to the next table to see the state of the backup batte ry and internal power supply ?s state of the ic by each condition. v cc v det1 v cc < v det1 vcc rtc, vdd vdcc =off(h) vsb rtc, vdd vdcc =l as a backup battery, not only a primary battery such as cr2025, lr44, or a secondary battery such as ml614, tc616, but also an electric double layered capacitor or an aluminum capacitor can be used. switchover point is judged with the voltage of the main power (vcc), theref ore, if the backup voltage is higher than main supply voltage, switchover can be realized withou t extra load to the backup power supply. vdd vsb vcc vss 0.1 f cpu power supply the case of back-up b y primary battery cr2025 etc. vsb vd d vc c vss 0.1 f cpu power supply ml614 etc. the case of back-up by capacitor or secondary battery (charging voltage is equal to cpu power supply voltage) vsb vd d vc c vss 0.1 f cpu power supply (3v) 5v double layer capacitor etc. the case of back-up by capacitor or secondary battery (charging voltage is not equal to cpu power supply voltage) ? interface with cpu the r2061 is connected to the cpu by three signal lines ce (chip enable), sclk (serial clock), and sio (serial input / output), through which it reads and writ es data from and to the cpu. the cpu can be accessed when the ce pin is held high. access clock pulses have a maximum frequency of 1 mhz, allowing high-speed data transfer to the cpu. vcc falls down under -v det1 , the r2061 stops accessing with cpu.
r2061 series 13 ? clock and calenda r function the r2061 reads and writes time data from and to the cpu in units ranging from seconds to the last two digits of the calendar year. the calendar year will automatically be i dentified as a leap year when its last two digits are a multiple of 4. consequently, leap years up to the year 2099 can automatically be identified as such. *) the year 2000 is a leap year while the year 2100 is not a leap year. ? alarm function the r2061 incorporates the alarm interrupt circuit configur ed to generate interrupt sig nals to the cpu at preset times. the alarm interrupt circuit allows two types of alarm settings specified by the alarm_w registers and the alarm_d registers. the alarm_w registers allow week, hour, and minute alarm settings including combinations of multiple day-of-week settings such as "monday , wednesday, and friday" and "saturday and sunday". the alarm_d registers allow hour and minute alarm settings. the alarm_w outputs from intr pin, and the alarm_d outputs also from intr pin. each alarm function can be chec ked from the cpu by using a polling function. ? high-precision oscillation adjustment function the r2061 has built-in oscillation stabi lization capacitors (cg and cd), that can be c onnected to an external quartz crystal unit to configure an oscillation circuit. two ki nds of accuracy for this f unction are alternatives. to correct deviations in the oscillator freque ncy of the crystal, the oscillation adj ustment circuit is configured to allow correction of a time count gain or loss (up to 1.5ppm or 0.5ppm at 25 c) from the cpu. the maximum range is approximately 189ppm (or 63ppm) in increments of approximately 3ppm (or 1ppm). such oscillation frequency adjustment in each system has the following advantages: * allows timekeeping with much high er precision than conventional rtcs while using a quartz crystal unit with a wide range of precision variations. * corrects seasonal frequency deviations through seasonal oscillation adjustment. * allows timekeeping with higher precision particularly with a temperature sensing function out of rtc, through oscillation adjustment in tune with temperature fluctuations. ? power-on reset, oscillation halt sensing function and supply voltage monitoring function the r2061 has 3 power supply pins (vcc, vsb, vdd) , among them, vcc pin and vdd pin have monitoring function of supply voltage. vcc power supply monitoring circuit makes vdcc pin ?l? when vcc power supply pin becomes equal or lower than ?v det1 . at the power-on of vcc, this circuit makes vdcc pin turn off, or ?h? after the delay time, t delay from when the vcc power supply pin becomes equal or more than +v det1 . the r2061 incorporates an oscillation halt sensing circuit equipped with inte rnal registers conf igured to record any past oscillation halt, the oscillation halt sensing circuit, vdd monitoring flag, and power-on reset flag are useful for judging the validity of time data. power on reset function reset the control resisters when the system is powered on from 0v. at the same time, the fact is memorized to the resister as a flag, thereby id entifying whether they are powered on from 0v or battery backed-up. the r2061 also incorporates a supply voltage monitoring circuit equipped with internal registers configured to record any drop in supply voltage below a certain thres hold value. supply voltage monitoring threshold settings can be selected between 2.1v and 1.35v through internal re gister settings. the sampling rate is normally 1s.
r2061 series 14 the oscillation halt sensing circuit is co nfigured to confirm the established inva lidation of time data in contrast to the supply voltage monitoring circuit intended to confirm t he potential invalidation of time data. further, the supply voltage monitoring circuit can be applied to battery supply voltage monitoring. ? periodic interrupt function the r2061 incorporates the periodic interrupt circuit conf igured to generate periodic interrupt signals aside from interrupt signals generated by the periodi c interrupt circuit for output from the intr pin. periodic interrupt signals have five selectable frequency settings of 2 hz (o nce per 0.5 seconds), 1 hz (once per 1 second), 1/60 hz (once per 1 minute), 1/3600 hz (once per 1 hour), an d monthly (the first day of every month). further, periodic interrupt signals also have two selectable waveforms, a normal pulse form (with a frequency of 2 hz or 1 hz) and special form adapted to interruption from th e cpu in the level mode (with second, minute, hour, and month interrupts). the condition of periodic interrupt signals can be monitored with using a polling function.
r2061 series 15 address mapping address register name d a t a a3a2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 second counter - *2) s40 s20 s10 s8 s4 s2 s1 1 0 0 0 1 minute counter - m40 m20 m10 m8 m4 m2 m1 2 0 0 1 0 hour counter - - h20 p/ a h10 h8 h4 h2 h1 3 0 0 1 1 day-of-week counter - - - - - w4 w2 w1 4 0 1 0 0 day-of-month counter - - d20 d10 d8 d4 d2 d1 5 0 1 0 1 month counter and century bit 19 /20 - - mo10 mo8 mo4 mo2 mo1 6 0 1 1 0 year counter y80 y40 y20 y10 y8 y4 y2 y1 7 0 1 1 1 oscillation adjustment register *3) dev *4) f6 f5 f4 f3 f2 f1 f0 8 1 0 0 0 alarm_w (minute register) - wm40 wm20 wm10 wm8 wm4 wm2 wm1 9 1 0 0 1 alarm_w (hour register) - - wh20 wp/ a wh10 wh8 wh4 wh2 wh1 a 1 0 1 0 alarm_w (day-of-week register) - ww6 ww5 ww4 ww3 ww2 ww1 ww0 b 1 0 1 1 alarm_d (minute register) - dm40 dm20 dm10 dm8 dm4 dm2 dm1 c 1 1 0 0 alarm_d (hour register) - - dh20 dp/ a dh10 dh8 dh4 dh2 dh1 d 1 1 0 1 - - - - - - - - e 1 1 1 0 control register 1 *3) wale dale 12 /24 scra tch2 test ct2 ct1 ct0 f 1 1 1 1 control register 2 *3) vdsl vdet xst pon *5) scra tch1 ctfg wafg dafg notes: * 1) all the data listed above accept both reading and writing. * 2) the data marked with "-" is invalid for writing and reset to 0 for reading. * 3) when the pon bit is set to 1 in control register 2, all the bits are reset to 0 in oscillation adjustment register, control register 1 and control register 2 excluding the xst bit. * 4) when dev=0, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss up to 1.5ppm. when dev=1, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss up to or 0.5ppm. * 5) pon is a power-on-reset flag.
r2061 series 16 register settings ? control register 1 (address eh) d7 d6 d5 d4 d3 d2 d1 d0 wale dale 12 /24 scra tch2 test ct2 ct1 ct0 (for writing) wale dale 12 /24 scra tch2 test ct2 ct1 ct0 (for reading) 0 0 0 0 0 0 0 0 default settings *) *) default settings: default value means read / writt en values when the pon bit is set to ?1? due to vdd power-on from 0 volts. (1) wale, dale alarm_w enable bit, alarm_d enable bit wale,dale description 0 disabling the alarm interrupt circui t (under the control of the settings of the alarm_w registers and the alarm_d registers). (default) 1 enabling the alarm interrupt circuit (under the control of the settings of the alarm_w registers a nd the alarm_d registers) (2) 12 /24 12 /24-hour mode selection bit 12 /24 description 0 selecting the 12-hour mode with a.m. and p.m. indications. (default) 1 selecting the 24-hour mode setting the 12 /24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively. 24-hour mode 12-hour mode 24-hour mode 12-hour mode 00 12 (am12) 12 32 (pm12) 01 01 (am 1) 13 21 (pm 1) 02 02 (am 2) 14 22 (pm 2) 03 03 (am 3) 15 23 (pm 3) 04 04 (am 4) 16 24 (pm 4) 05 05 (am 5) 17 25 (pm 5) 06 06 (am 6) 18 26 (pm 6) 07 07 (am 7) 19 27 (pm 7) 08 08 (am 8) 20 28 (pm 8) 09 09 (am 9) 21 29 (pm 9) 10 10 (am10) 22 30 (pm10) 11 11 (am11) 23 31 (pm11) setting the 12 /24 bit should precede writing time data (3) scratch2 scratch bit 2 scratch2 description 0 (default) 1 the scratch2 bit is intended for scratching an d accepts the reading and writing of 0 and 1. the scratch2 bit will be set to 0 when the pon bi t is set to 1 in the control register 1.
r2061 series 17 (4) test test bit test description 0 normal operation mode. (default) 1 test mode. the test bit is used only for testing in the factory and should normally be set to 0. (5) ct2,ct1, and ct0 periodic interrupt selection bits description ct2 ct1 ct0 wave form mode interrupt cycle and falling timing 0 0 0 - off(h) (default) 0 0 1 - fixed at ?l? 0 1 0 pulse mode *1) 2hz(duty50%) 0 1 1 pulse mode *1) 1hz(duty50%) 1 0 0 level mode *2) once per 1 second (synchronized with second counter increment) 1 0 1 level mode *2) once per 1 minute (at 00 seconds of every minute) 1 1 0 level mode *2) once per hour (at 00 minutes and 00 seconds of every hour) 1 1 1 level mode *2) once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month) * 1) pulse mode: 2-hz and 1-hz clock pulses are out put in synchronization with the increment of the second counter as illustrated in the timing chart below. intr pin rewriting of the second counter ctfg bit a pprox. 92 s (increment of second counter) in the pulse mode, the increment of the second counter is delayed by approximately 92 s from the falling edge of clock pulses. consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. rewriting the second counter will reset the other time counters of less than 1 second, driving the intr pin low. * 2) level mode: periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. the increment of the second counter is synchronized with the falling edge of periodic interrupt signals. for example, periodi c interrupt signals with an interrupt cycle setting of 1 second are output in synchron ization with the increment of the second counter as illustrated in the timing chart below.
r2061 series 18 (increment of second counter) setting ctfg bit to 0 setting ctfg bit to 0 (increment of second counter) (increment of second counter) ctfg bit intr pin *1), *2) when the oscillation adjustment circuit is used, the interrupt cycl e will fluctuate once per 20sec. or 60sec. as follows: pulse mode: the ?l? period of output pulses will increment or decrement by a maximum of 3.784 ms. for example, 1-hz clock pulses will have a duty cycle of 50 0.3784%. level mode: a periodic interrupt cycle of 1 second will increment or decrement by a maximum of 3.784 ms.
r2061 series 19 ? control register 2 (address fh) d7 d6 d5 d4 d3 d2 d1 d0 vdsl vdet xst pon scra tch1 ctfg wafg dafg (for writing) vdsl vdet xst pon scra tch1 ctfg wafg dafg (for reading) 0 0 indefinite 1 0 0 0 0 default settings *) *) default settings: default value means read / writt en values when the pon bit is set to ?1? due to vdd power-on from 0 volts. (1) vdsl vdd supply voltage monitoring threshold selection bit vdsl description 0 selecting the vdd supply voltage monitori ng threshold setting of 2.1v. (default) 1 selecting the vdd supply voltage monitoring threshold setting of 1.35v. the vdsl bit is intended to select the vdd supply voltage monitoring threshold settings. (2) vdet supply voltage monitoring result indication bit vdet description 0 indicating supply voltage above the supply voltage monitoring threshold settings. (default) 1 indicating supply voltage below the supply voltage monitoring threshold settings. once the vdet bit is set to 1, the supply voltage moni toring circuit will be disabled while the vdet bit will hold the setting of 1. the vdet bit accepts only t he writing of 0, which restarts the supply voltage monitoring circuit. conversely, setting the vdet bit to 1 causes no event. (3) xst oscillation halt sensing monitor bit xst description 0 sensing a halt of oscillation 1 sensing a normal condition of oscillation the xst accepts the reading and writing of 0 and 1. the xst bit will be set to 0 when the oscillation halt sensing. the xst bit will hold 0 even after t he restart of oscillation. (4) pon power-on-reset flag bit pon description 0 normal condition 1 detecting vdd power-on -reset (default) the pon bit is for sensing power-on reset condition. * the pon bit will be set to 1 when vdd power-on from 0 volts. the pon bit will hold the setting of 1 even after power-on. * when the pon bit is set to 1, all bits will be reset to 0, in the os cillation adjustment register, control register 1, and control register 2, except xst and pon. as a result, intr pin stops outputting. * the pon bit accepts only the writing of 0. conv ersely, setting the pon bit to 1 causes no event.
r2061 series 20 (5) scratch1 scratch bit 1 scratch1 description 0 (default) 1 the scratch1 bit is intended for scratching and accepts the reading and writing of 0 and 1. the scratch1 bit will be set to 0 when the pon bit is set to 1 in the control register 2. (6) ctfg periodic interrupt flag bit ctfg description 0 periodic interrupt output = ?h? (default) 1 periodic interrupt output = ?l? the ctfg bit is set to 1 when the peri odic interrupt signals are output from the intr pin (?l?). the ctfg bit accepts only the writing of 0 in the level mode, which disables (?h?) the intr pin until it is enabled (?l?) again in the next interrupt cycle. conver sely, setting the ctfg bit to 1 causes no event. (7) wafg,dafg alarm_w flag bit and alarm_d flag bit wafg,dafg description 0 indicating a mismatch between current time and preset alarm time (default) 1 indicating a match between current time and preset alarm time the wafg and dafg bits are valid only when the wale and dale have the setting of 1, which is caused approximately 61 s after any match between current time and pr eset alarm time specified by the alarm_w registers and the alarm_d regist ers. the wafg (dafg) bit ac cepts only the writing of 0. intr pin outputs off (?h?) when this bit is set to 0. and intr pin outputs ?l? again at the next preset alarm time. conversely, setting the wafg and dafg bits to 1 ca uses no event. the wafg and dafg bits will have the reading of 0 when the alarm interrupt circuit is disa bled with the wale and dale bits set to 0. the settings of the wafg and dafg bits ar e synchronized with the output of the intr pin as shown in the timing chart below. intr pin writing of 0 to wafg(dafg) bit wafg(dafg) bit (match between current time and preset alarm time) a pprox. 61 s a pprox. 61 s writing of 0 to wafg(dafg) bit (match between current time and preset alarm time) (match between current time and preset alarm time)
r2061 series 21 ? time counter (address 0-2h) second counter (address 0h) d7 d6 d5 d4 d3 d2 d1 d0 - s40 s20 s10 s8 s4 s2 s1 (for writing) 0 s40 s20 s10 s8 s4 s2 s1 (for reading) 0 indefinite indefinite indefin ite indefinite indefinite indefinite i ndefinite default settings *) minute counter (address 1h) d7 d6 d5 d4 d3 d2 d1 d0 - m40 m20 m10 m8 m4 m2 m1 (for writing) 0 m40 m20 m10 m8 m4 m2 m1 (for reading) 0 indefinite indefinite indefin ite indefinite indefinite indefinite i ndefinite default settings *) hour counter (address 2h) d7 d6 d5 d4 d3 d2 d1 d0 - - p/ a or h20 h10 h8 h4 h2 h1 (for writing) 0 0 p/ a or h20 h10 h8 h4 h2 h1 (for reading) 0 0 indefinite indefinite indefinite indefinit e indefinite indefinite default settings *) *) default settings: default value means read / wri tten values when the pon bit is set to ?1? due to vdd power-on from 0 volts. * time digit display (bcd format) as follows: the second digits range from 00 to 59 and are carri ed to the minute digit in transition from 59 to 00. the minute digits range from 00 to 59 and are carri ed to the hour digits in transition from 59 to 00. the hour digits range as shown in "p16 ? control register 1 (address eh) (2) 12 /24: 12 /24-hour mode selection bit" and are carried to the day-of-mont h and day-of-week digits in transition from pm11 to am12 or from 23 to 00. * any writing to the second counter resets divider units of less than 1 second. * any carry from lower digits with the writing of non-existent time may cause the time counters to malfunction. therefore, such incorrect writing should be replaced with the writing of existent time data.
r2061 series 22 ? day-of-week counter (address 3h) d7 d6 d5 d4 d3 d2 d1 d0 - - - - - w4 w2 w1 (for writing) 0 0 0 0 0 w4 w2 w1 (for reading) 0 0 0 0 0 indefinite indefinite indefinite default settings *) *) default settings: default value means read / wri tten values when the pon bit is set to ?1? due to vdd power-on from 0 volts. * the day-of-week counter is increm ented by 1 when the day-of-week digi ts are carried to the day-of-month digits. * day-of-week display (incremented in septimal notation): (w4, w2, w1) = (0, 0, 0) (0, 0, 1) ? (1, 1, 0) (0, 0, 0) * correspondences between days of the week an d the day-of-week digits are user-definable (e.g. sunday = 0, 0, 0) * the writing of (1, 1, 1) to (w4, w2, w1) is pr ohibited except when days of the week are unused. ? calendar counter (address 4-6h) day-of-month counter (address 4h) d7 d6 d5 d4 d3 d2 d1 d0 - - d20 d10 d8 d4 d2 d1 (for writing) 0 0 d20 d10 d8 d4 d2 d1 (for reading) 0 0 indefinite indefinite indefinite indefinit e indefinite indefinite default settings *) month counter + century bit (address 5h) d7 d6 d5 d4 d3 d2 d1 d0 19 /20 - - mo10 mo8 mo4 mo2 mo1 (for writing) 19 /20 0 0 mo10 mo8 mo4 mo2 mo1 (for reading) indefinite 0 0 indefinite indefin ite indefinite indefinite indefinite default settings *) year counter (address 6h) d7 d6 d5 d4 d3 d2 d1 d0 y80 y40 y20 y10 y8 y4 y2 y1 (for writing) y80 y40 y20 y10 y8 y4 y2 y1 (for reading) indefinite indefinite indefinite i ndefinite indefinite indefinite indefinit e indefinite default settings *) *) default settings: default value means read / writt en values when the pon bit is set to ?1? due to vdd power-on from 0 volts. * the calendar counters are configured to display the calendar digits in bcd format by using the automatic calendar function as follows: the day-of-month digits (d20 to d1) range from 1 to 31 for january, march, may, july, august, october, and december; from 1 to 30 for april, june, september, and november; from 1 to 29 for february in leap years; from 1 to 28 for february in ordinary years. the day-of-month digits are carried to the month digits in reversion from the last day of the month to 1. the month digits (mo10 to mo1) range from 1 to 12 and are carried to the year digits in reversion from 12 to 1.
r2061 series 23 the year digits (y80 to y1) range from 00 to 99 (00, 04, 08, , 92, and 96 in leap years) and are carried to the 19 /20 digits in reversion from 99 to 00. the 19 /20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits. * any carry from lower digits with the writing of non-existent calendar data may cause the calendar counters to malfunction. therefore, such incorrect writing should be repl aced with the writing of existent calendar data. ? oscillation adjustment register (address 7h) d7 d6 d5 d4 d3 d2 d1 d0 dev f6 f5 f4 f3 f2 f1 f0 (for writing) dev f6 f5 f4 f3 f2 f1 f0 (for reading) 0 0 0 0 0 0 0 0 default settings *) *) default settings: default value means read / writt en values when the pon bit is set to ?1? due to vdd power-on from 0 volts. dev bit when dev is set to 0, the oscillati on adjustment circuit operates 00, 20, 40 seconds. when dev is set to 1, the oscillation adjustment circuit operates 00 seconds. f6 to f0 bits the oscillation adjustment circuit is config ured to change time counts of 1 second on the basis of the settings of the oscillation adjustment register at the timing set by dev. * the oscillation adjustment circuit will not oper ate with the same timing (00, 20, or 40 seconds) as the timing of writing to t he oscillation adjustment register. * the f6 bit setting of 0 causes an increment of ti me counts by ((f5, f4, f3, f2, f1, f0) - 1) x 2. the f6 bit setting of 1 causes a decrement of time counts by (( f 5 , f 4 , f 3 , f 2 , f 1 , f 0 ) + 1) x 2. the settings of "*, 0, 0, 0, 0, 0, *" ("*" repr esenting either "0" or "1") in the f6, f5, f4, f3, f2, f1, and f0 bits cause neither an increment nor decrement of time counts. example: if (dev, f6, f5, f4, f3, f2, f1, f0) is set to (0, 0, 0, 0, 0, 1, 1, 1), when the second digits read 00, 20, or 40, an increment of the current time counts of 32768 + (7 - 1) x 2 to 32780 (a current time count loss). if (dev, f6, f5, f4, f3, f2, f1, f0) is set to (0, 0, 0, 0, 0, 0, 0, 1), when the second digits read 00, 20, 40, neither an increment nor a decrement of the current time counts of 32768. if (dev, f6, f5, f4, f3, f2, f1, f0) is set to (1, 1, 1, 1, 1, 1, 1, 0), when the second digits read 00, a decrement of the current time counts of 32768 + (- 2) x 2 to 32764 (a current time count gain). an increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3 ppm (2 / (32768 x 20 = 3.051 ppm). conversely, a decrease of two clock pulses once per 20 seconds causes a time count gain of 3 ppm. consequently, when dev is set to ?0?, deviations in time counts can be corrected with a precision of 1.5 ppm. in the same way, when dev is set to ?1?, deviations in time counts can be corrected with a precision of 0.5 ppm. note that the oscillation adjustment circuit is configured to correct devia tions in time counts and not the osc illation frequency of the 32.768-khz clock pulses. for further details, see "p35 configuration of oscillation circ uit and correction of time count deviations ? oscillation adjustment circuit ".
r2061 series 24 ? alarm_w registers (address 8-ah) alarm_w minute register (address 8h) d7 d6 d5 d4 d3 d2 d1 d0 - wm40 wm20 wm10 wm8 wm4 wm2 wm1 (for writing) 0 wm40 wm20 wm10 wm8 wm4 wm2 wm1 (for reading) 0 indefinite indefinite indefinite indefinite indefinite indefinite indefinite default settings *) alarm_w hour register (address 9h) d7 d6 d5 d4 d3 d2 d1 d0 - - wh20 wp/ a wh10 wh8 wh4 wh2 wh1 (for writing) 0 0 wh20 wp/ a wh10 wh8 wh4 wh2 wh1 (for reading) 0 0 indefinite indefinite i ndefinite indefinite indefinite indefinite default settings *) alarm_w day-of-week register (address ah) d7 d6 d5 d4 d3 d2 d1 d0 - ww6 ww5 ww4 ww3 ww2 ww1 ww0 (for writing) 0 ww6 ww5 ww4 ww3 ww2 ww 1 ww0 (for reading) 0 indefinite indefinite indefinite i ndefinite indefinite indefinite indefinite default settings *) *) default settings: default value means read / writt en values when the pon bit is set to ?1? due to vdd power-on from 0 volts. * the d5 bit of the alarm_w hour register represents wp/ a when the 12-hour mode is selected (0 for a.m. and 1 for p.m.) and wh20 when the 24-hour mode is selected (tens in the hour digits). * the alarm_w registers should not have any non-existent alarm time settings. (note that any mismatch between current time and pres et alarm time specified by the alarm_w registers may disable the alarm interrupt circuit.) * when the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively. (see "p16 ? control register 1 (address eh) (2) 12 /24: 12 /24-hour mode selection bit") * ww0 to ww6 correspond to w4, w2, and w1 of the day-o f-week counter with settings ranging from (0, 0, 0) to (1, 1, 0). * ww0 to ww6 with respective settings of 0 disable the outputs of t he alarm_w registers.
r2061 series 25 example of alarm time setting alarm day-of-week 12-hour mode 24-hour mode preset alarm time sun. mon. tue. wed. th. fri. sat. 10 hr. 1 hr. 10 min. 1 min. 10 hr. 1 hr. 10 min. 1 min. ww0 ww1 ww2 ww3 ww4 ww5 ww6 00:00 a.m. on all days 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 01:30 a.m. on all days 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 11:59 a.m. on all days 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 00:00 p.m. on mon. to fri. 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0 01:30 p.m. on sun. 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0 11:59 p.m. on mon. ,wed., and fri. 0 1 0 1 0 1 0 3 1 5 9 2 3 5 9 note that the correspondence bet ween ww0 to ww6 and the day s of the week shown in the above table is only an example and not mandatory. ? alarm_d register (address b-ch) alarm_d minute register (address bh) d7 d6 d5 d4 d3 d2 d1 d0 - dm40 dm20 dm10 dm8 dm4 dm2 dm1 (for writing) 0 dm40 dm20 dm10 dm8 dm4 dm2 dm1 (for reading) 0 indefinite indefinite indefin ite indefinite indefinite indefinite i ndefinite default settings *) alarm_d hour register (address ch) d7 d6 d5 d4 d3 d2 d1 d0 - - dh20 dp/ a dh10 dh8 dh4 dh2 dh1 (for writing) 0 0 dh20 dp/ a dh10 dh8 dh4 dh2 dh1 (for reading) 0 0 indefinite indefinite indefinite indefinit e indefinite indefinite default settings *) *) default settings: default value means read / writt en values when the pon bit is set to ?1? due to vdd power-on from 0 volts. * the d5 bit represents dp/ a when the 12-hour mode is selected (0 for a.m. and 1 for p.m.) and dh20 when the 24-hour mode is selected (tens in the hour digits). * the alarm_d registers should not have any non-existent alarm time settings. (note that any mismatch between current time and pr eset alarm time specified by the alarm_d registers may disable the alarm interrupt circuit.) * when the 12-hour mode is selected, the hour digits read 12 and 32 for 0a.m. and 0p.m., respectively. (see "p16 ? control register 1 (address eh) (2) 12 /24: 12 /24-hour mode selection bit")
r2061 series 26 interfacing with the cpu ? data transfer formats (1) timing between ce pin transition and data input / output the r2061 adopts a 3-wire serial interface by which t hey use the ce (chip enable), sclk (serial clock), and sio (serial input/output) pins to receive and send data to and from the cpu. the 3-wire serial interface provides two types of input/output timings with which the sio pin output and input are synchronized with the rising or falling edges of the sclk pin input, respectively, and vice versa. the r2061 is configured to select either one of two different input/output timings depending on the level of the sclk pin in the low to high transition of the ce pin. namely, when the sclk pin is held low in the low to high transition of the ce pin, the models will select the timing with which the sio pin output is synchronized with the ri sing edge of the sclk pin input, and the input is synchronized with the falling edge of the sclk pin input, as illustrated in the timing chart below. sclk sio (for reading) t ds sio (for writing) ce t ces t dh t rd conversely, when the sclk pin is held high in the low to high transition of the ce pin, the models will select the timing with which the sio pin output is synchronized with the falling edge of the sclk pin input, and the input is synchronized with the rising edge of the sclk pi n input, as illustrated in the timing chart below. sclk sio (for reading) t ds sio (for writing) ce t ces t dh t rd
r2061 series 27 (2) data transfer formats data transfer is commenced in the low to high transition of the ce pin input and completed in its high to low transition. data transfer is conducted serially in multiple units of 1 byte (8 bits). the former 4 bits are used to specify in the address pointer a head address with which data transfer is to be commenced from the host. the latter 4 bits are used to select either reading data transfe r or writing data transfer, and to set the transfer format register to specify an appropriate data transfer format. all data transfer formats are designed to transfer the most significant bit (msb) first. a2 ce scl k 6 a1 a0 c3 c2 c1 c0 a3 7 5823 1 23 14 d7 d6 d3 d2 d1 d0 setting the address pointer writing or reading data transfer setting the transfer format register sio two types of data transfer formats are available for reading data transfer and writing data transfer each. ? writing data transfer formats (1) 1-byte writing data transfer format the first type of writing data transfer format is designed to transfer 1-byte data at a time and can be selected by specifying in the address pointer a head address with which writing data transfer is to be commenced and then writing the setting of 8h to the transfer format register. this 1-byte writing data transfer can be completed by driving the ce pin low or continue d by specifying a new head address in the address pointer and setting the data transfer format. 1 1 data data example of 1-byte writing data transfer (for writing data to addresses fh and 7h) data transfer from the host ce data transfer from the rtcs specifying 7h in the a ddress pointer 0 1 0 0 1 1 setting 8h in the transfer format register writing data to address fh writing data to address 7h 0 1 1 0 0 0 1 1 specifying fh in the a ddress pointer setting 8h in the transfer format register sio
r2061 series 28 (2) burst writing data transfer format the second type of writing data transfer format is desi gned to transfer a sequence of data serially and can be selected by specifying in the address pointer a head add ress with which writing data transfer is to be commenced and then writing the setting of 0h to the tran sfer format register. the address pointer is incremented for each transfer of 1-byte data and cycled from fh to 0h. this burst writing data transfer can be completed by driving the ce pin low. 1 0 data data example of burst writing data transfer (for writing data to addresses eh, fh, and 0h) ce 0 0 0 0 1 1 sio data data transfer from the host data transfer from the rtcs writing data to address eh specifying eh in the a ddress pointer setting 0h in the transfer format register writing data to address fh writing data to address 0h ? reading data transfer formats (1) 1-byte reading data transfer format the first type of reading data transfer format is designed to transfer 1-byte data at a time and can be selected by specifying in the address pointer a head address with which reading data transfer is to be commenced and then the setting of writing ch to the transf er format register. this 1-byte reading data transfer can be completed by driving the ce pin low or continued by specifying a ne w head address in the address pointer and selecting this type of reading data transfer format. 1 0 data data example of 1-byte reading data transfer (for reading data from addresses eh and 2h) ce 1 1 0 0 1 1 0 1 0 1 0 0 0 1 sio data transfer from the host data transfer from the rtcs specifying 2h in the a ddress pointer setting ch in the transfer format register reading data from address eh reading data from address 2h specifying eh in the a ddress pointer setting ch in the transfer format register
r2061 series 29 (2) burst reading data transfer format the second type of reading data transfer format is desig ned to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which reading data transfer is to be commenced and then writing the setting of 4h to the tran sfer format register. the address pointer is incremented for each transfer of 1-byte data and cycled from fh to 0h. this burst reading data transfer can be completed by driving the ce pin low. 1 1 data data example of burst reading data transfer (for reading data from addresses fh, 0h, and 1h) ce 1 0 0 0 1 1 data sio data transfer from the host data transfer from the rtcs reading data from address fh specifying fh in the a ddress pointer setting 4h in the transfer format register reading data from address 0h reading data from address 1h (3) combination of 1-byte reading and writing data transfer formats the 1-byte reading and writing data transfer formats can be combined together and further followed by any other data transfer format. 1 1 data example of reading modify writing data transfer (for reading and writing data from and to address fh) ce 1 1 0 0 1 1 1 1 1 0 0 0 1 1 data sio data transfer from the host data transfer from the rtcs writing data to address fh specifying fh in the a ddress pointer setting 8h in the transfer format register specifying fh in the a ddress pointer setting ch in the transfer format register reading data from address fh the reading and writing data transfer formats correspond to the settings in the transfer format register as shown in the table below. 1 byte burst writing data transfer 8h (1,0,0,0) 0h (0,0,0,0) reading data transfer ch (1,1,0,0) 4h (0,1,0,0)
r2061 series 30 ? considerations in reading and writing time data under special condition any carry to the second digits in the process of read ing or writing time data may cause reading or writing erroneous time data. for example, suppose a carry ou t of 13:59:59 into 14:00:00 o ccurs in the process of reading time data in the middle of shifting from the minute digits to the hour digits. at this moment, the second digits, the minute digits, and the hour digits read 59 seco nds, 59 minutes, and 14 hours, respectively (indicating 14:59:59) to cause the reading of time data deviating from actual time virtually 1 hour. a similar error also occurs in writing time data. to prevent such errors in reading and writing time data, the r2061 has the function of temporarily locking any carry to the second digits durin g the high interval of the ce pin and unlocking such a carry in its high to low transition. note that a carry to the second digits can be locked for only 1 second, during which time the ce pin should be driven low. ce time counts within rtc 14:00:01 actual time 13:59:59 max.62 s 14:00:00 13:59:59 14:00:00 14:00:01 the effective use of this function requires the followi ng considerations in reading and writing time data: (1) hold the ce pin high in each session of reading or writing time data. (2) ensure that the high interval of the ce pin lasts within 1 second. s hould there be any possibility of the host going down in the process of reading or writing time data, make arrangements in the peripheral circuitry as to drive the ce pin low or open at the mom ent that the host actually goes down. (3) leave a time span of 31 s or more from the low to high transition of the ce pin to the start of access to addresses 0h to 6h in order that any ongoing carry of the time digits may be completed within this time span. (4) leave a time span of 62 s or more from the high to low transition of the ce pin to its low to high transition in order that any ongoing carry of the time digits during the high interval of the ce pin may be adjusted within this time span. the considerations listed in (1), (3), and (4) above are not required when the process of reading or writing time data is obviously free from any carry of the time digits. (e.g. reading or writing time data in synchronization with the periodic interrupt function in the level mode or the alarm interrupt function). good and bad examples of reading and writing ti me data are illustrated on the next page.
r2061 series 31 0ch data data bad example (1) (where the ce pin is once driven low in the process of reading time data) less than 62 s f0h ce time span of less than 31 s writing to a ddress 0h (sec.) 0ch ce bad example (3) (where a time span of less than 62 s is left between the adjacent processes of reading time data) good example data f4h data data ce a ddress pointer = 1h transfer format register = 4h time span of 31 s or more reading from a ddress 1h (min.) data 0ch data data 31 s or more reading from a ddress 1h (min.) data 14h 31 s or more ce data transfer from rtcs 0ch data data transfer from the host bad example (2) (where a time span of less than 31 s is left until the start of the process of writing time data) a ny address other than addresses 0h to 6h permits of immediate reading or writing withou t requiring a time span of 31 s. sio sio sio sio data data data data reading from a ddress fh (control2) reading from a ddress 0h (sec.) reading from a ddress 2h (hr.) a ddress pointer = fh transfer format register = 4h a ddress pointer = fh transfer format register = 0h reading from a ddress 0h (sec.) reading from a ddress 2h (hr.) a ddress pointer = 0h transfer format register = ch writing to a ddress 1h (min.) writing to a ddress 2h (hr.) writing to a ddress fh (contorl2) a ddress pointer = 0h transfer format register = ch reading from a ddress 0h (sec.) reading from a ddress 0h (sec.) a ddress pointer = 0h transfer format register = ch
r2061 series 32 configuration of oscillation circui t and correction of time count deviations ? configuration of oscillation circuit 32khz cg cd a oscin oscout oscillator circuit the oscillation circuit is driven at a constant voltage of appr oximately 1.2 volts relative to the level of the vss pin input. as such, it is configured to generate an oscillati ng waveform with a peak-to-peak voltage on the order of 1.1 volts on the positive side of the vss pin input. < considerations in handling quartz crystal units > generally, quartz crystal units have basic characteristics including an equivalent series resistance (r1) indicating the ease of their oscillation and a lo ad capacitance (cl) indicating the de gree of their center frequency. particularly, quartz crystal units intended for use in the r2061 are recommended to have a typical r1 value of 30k ? and a typical cl value of 6 to 8pf. to confirm these recommended values, contact the manufacturers of quartz crystal units intended for use in these particular models. < considerations in installing compo nents around the oscillation circuit > 1) install the quartz crystal unit in the closes t possible vicinity to the real-time clock ics. 2) avoid laying any signal lines or power lines in the vici nity of the oscillation circuit (particularly in the area marked "a" in the above figure). 3) apply the highest possible insulation resistance between the oscin and oscout pins and the printed circuit board. 4) avoid using any long parallel lines to wire the oscin and oscout pins. 5) take extreme care not to cause condensation, whic h leads to various problems such as oscillation halt. < other relevant considerations > 1) we cannot recommend connecting the external in put of 32.768-khz clock pul ses to the oscin pin. 2) to maintain stable characteristics of the quartz cr ystal unit, avoid driving any other ic through 32.768-khz clock pulses output from the oscout pin. typical externally-equipped element x?tal : 32.768khz (r1=30k ? typ) (cl=6pf to 8pf) standard values of internal elements cg,cd 10pf typ
r2061 series 33 ? measurement of oscillation frequency frequency counter 32768hz vcc oscin oscout vdd intr vss * 1) the r2061 is configured to generat e 1hz clock pulses for output from the intr pin by setting (00xx0011) at address eh. * 2) a frequency counter with 6 (more preferably 7) or more digits on the order of 1ppm is recommended for use in the measurement of the oscillation frequency of the oscillation circuit. ? adjustment of oscillation frequency the oscillation frequency of the oscillation circuit can be adjusted by varying procedures depending on the usage of model r2061 in the system into which they ar e to be built and on the allowable degree of time count errors. course (a) when the time count precision of each rtc is not to be adjusted, the quartz crystal unit intended for use in that rtc may have any cl value requiring no presetting. the quartz crystal unit may be subject to frequency variations which are selectable within the allowable range of time count precision. several quartz crystal units and rtcs should be used to find the center frequency of the quartz crystal units by the method described in "p33 ? measurement of oscillation frequency" and then calc ulate an appropriate oscillation adjustment value by the method described in "p35 ? oscillation adjustment circuit" for writing this value to the r2061. course (b) when the time count precision of each rtc is to be adj usted within the oscillation frequency variations of the quartz crystal unit plus the frequency variations of the real-time clock ics, it bec omes necessary to correct deviations in the time count of each rtc by the method described in " p35 ? oscillation adjustment circuit". such oscillation adjustment provides quartz crystal units with a wider range of allowable settings of their oscillation frequency variations and their cl values. the real-time clock ic and the quartz crystal unit intended for use in that real-time clock ic should be used to find the center frequency of the quartz crystal unit by the method described in " p33 ? measurement of oscillation frequency " and then confirm the center frequency thus found to fall within th e range adjustable by the o scillation adjustment circuit before adjusting the oscillation frequency of the oscillation circuit. at normal temperatur e, the oscillation frequency of the oscillator circuit can be adjusted by up to approximately 0.5ppm. * 1) generally, quartz crystal units for commercial us e are classified in terms of their center frequency
r2061 series 34 depending on their load capacitance (cl) and further divided into ranks on the order of 10, 20, and 50ppm depending on the degree of thei r oscillation frequency variations. * 2) basically, model r2061 is configured to cause frequency variations on the order of 5 to 10ppm at 25 c. * 3) time count precision as referred to in the above flow chart is applicable to normal temperature and actually affected by the temperature characteristic s and other properties of quartz crystal units. the r2061, which incorporate the cg and the cd, requi re adjusting the oscillation frequency of the quartz crystal unit through its cl value. generally, the relationship between the cl value and the cg and cd values can be represented by the following equation: cl = (cg cd)/(cg + cd) + cs where "cs" represents the floating capacity of the printed circuit board. the quartz crystal unit intended for use in the r2061 is recommended to have the cl value on the order of 6 to 8pf. its oscillation frequency should be measur ed by the method described in " p33 ? measurement of oscillation frequency". any quartz crystal unit found to have an excessively high or low oscillation frequency (causing a time count gain or loss, respectively) shoul d be replaced with another one having a smaller and greater cl value, respectively until another one having an opt imum cl value is selected. in this case, the bit settings disabling the oscillation adjustment circuit (see " p35 ? oscillation adjustment circuit ") should be written to the oscillation adjustment register. incidentally, the high oscillation frequency of the quartz crystal unit can also be adjusted by adding an external oscillation stabilization capa citor cgout as illustrated in the diagram below. 32khz rd cg cd oscin oscout cgout *1) oscillator circuit *1) the cgout should have a capacitance ranging from 0 to 15 pf.
r2061 series 35 ? oscillation adjustment circuit the oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying the number of 1-second clock pulses once per 20 second s or 60 seconds. when dev bit in the oscillation adjustment register is set to 0, r2061 varies number of 1-second clock pulses once per 20 seconds. when dev bit is set to 1, r2061 varies number of 1-second clock pulses once per 60 seconds. the oscillation adjustment circuit can be disabled by writing the settings of "*, 0, 0, 0, 0, 0, *" ("*" r epresenting "0" or "1") to the f6, f5, f4, f3, f2, f1, and f0 bits in the oscillation adjustment circuit. conversely, when such oscillation adjustment is to be made, an appropriate oscillation adju stment value can be calculated by the equation below for writing to the oscillation adjustment circuit. (1) when oscillation frequency (* 1) is higher than target frequency (* 2) (causing time count gain) when dev=0: oscillation adjustment value (*3) = (oscillation frequency - target frequency + 0.1) oscillation frequency 3.051 10 -6 (oscillation frequency ? target frequency) 10 + 1 when dev=1: oscillation adjustment value (*3) = (oscillation frequency - target frequency + 0.0333) oscillation frequency 1.017 10 -6 (oscillation frequency ? target frequency) 30 + 1 * 1) oscillation frequency: 32768 times the frequency of 1hz clock pulse output from the intr pin at normal temperature in the manner described in " p33 ? measurement of oscillation frequency". * 2) target frequency: desired frequency to be set. generally, a 32.768-khz quartz crystal unit has such temperature characteristics as to have the highest oscillation frequency at normal temperature. consequently, the quartz crystal unit is recommended to have ta rget frequency settings on the order of 32.768 to 32.76810 khz (+3.05ppm relative to 32.768 khz). note that the target frequency differs depending on the environment or location where the equipment incorporating the rtc is expected to be operated. * 3) oscillation adjustment value: value that is to be finally written to the f0 to f6 bits in the oscillation adjustment register and is represented in 7-bit coded decimal notation. (2) when oscillation frequency is equal to target fr equency (causing time count neither gain nor loss) oscillation adjustment value = 0, +1, -64, or ?63
r2061 series 36 (3) when oscillation frequency is lower than target frequency (causing time count loss) when dev=0: oscillation adjustment value = (oscilla tion frequency - target frequency) oscillation frequency 3.051 10 -6 (oscillation frequency ? target frequency) 10 when dev=1: oscillation adjustment value = (oscilla tion frequency - target frequency) oscillation frequency 1.017 10 -6 (oscillation frequency ? target frequency) 30 oscillation adjustment value calcul ations are exemplified below (a) for an oscillation frequency = 32768.85hz and a target frequency = 32768.05hz when setting dev bit to 0: oscillation adjustment value = (32768.85 - 32768.05 + 0.1) / (32768.85 3.051 10 -6 ) (32768.85 - 32768.05) 10 + 1 = 9.001 9 in this instance, write the settings (dev,f6,f5,f4,f3,f 2,f1,f0)=(0,0,0,0,1,0,0,1) in the oscillation adjustment register. thus, an appropriate oscillation adjustment val ue in the presence of any time count gain represents a distance from 01h. when setting dev bit to 1: oscillation adjustment value = (32768.85 - 32768.05 + 0.0333) / (32768.85 1.017 10 -6 ) (32768.85 - 32768.05) 30 + 1 = 25.00 25 in this instance, write the settings (dev,f6,f5,f4,f3,f 2,f1,f0)=(1,0,0,1,1,0,0,1) in the oscillation adjustment register. (b) for an oscillation frequency = 32762.22hz and a target frequency = 32768.05hz when setting dev bit to 0: oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 3.051 10 -6 ) (32762.22 - 32768.05) 10 = -58.325 -58 to represent an oscillation adjustment value of - 58 in 7- bit coded decimal notation, subtract 58 (3ah) from 128 (80h) to obtain 46h. in this instance, write the settings of (dev,f6,f5,f4,f3,f2,f1,f0) = (0,1,0,0,0,1,1,0) in the oscillation adjustment register. thus, an appropriate os cillation adjustment value in the presence of any time count loss represents a distance from 80h. when setting dev bit to 1: oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 1.017 10 -6 ) (32762.22 - 32768.05) 30 = -174.97 -175 oscillation adjustment value can be set from -62 to 63. then, in this case, oscillation adjustment value is out of range.
r2061 series 37 (4) difference between dev=0 and dev=1 difference between dev=0 and dev=1 is following, dev=0 dev=1 maximum value range -189.2ppm to 189.2ppm -62ppm to 63ppm minimum resolution 3ppm 1ppm notes: if following 3 conditions are completed, actual clock adjustment value could be different from target adjustment value that set by oscillator adjustment function. 1. using oscillator adjustment function 2. access to r2061 at random, or synchronized with external clock that has no relation to r2061, or synchronized with periodic interrupt in pulse mode. 3. access to r2061 more than 2 times per each second on average. for more details, please contact to ricoh. ? how to evaluate the clock gain or loss the oscillator adjustment circuit is co nfigured to change time co unts of 1 second on the basis of the settings of the oscillation adjustment register on ce in 20 seconds or 60 seconds. t he way to measure the clock error as follows: (1) output a 1hz clock pulse of pulse mode with interrupt pin set (0,0,x,x,0,0,1,1) to control register 1 at address eh. (2) after setting the oscillation adjustment register, 1hz clock period change s every 20seconds ( or every 60 seconds) like next page figure. 1hz clock pulse t0 t0 t0 t1 1 time 19 times measure the interval of t0 and t1 with frequency count er. a frequency counter with 7 or more digits is recommended for the measurement. (3) calculate the typical period from t0 and t1 t = (19 t0+1 t1)/20 calculate the time error from t.
r2061 series 38 power-on reset, oscillation halt sensing, and supply voltage monitoring ? pon, xst , and vdet the power-on reset circuit is configured to reset cont rol register1, 2, and clock adjustment register when vdd power up from 0v. the oscillation halt sensing circuit is configured to record a halt on oscillation by 32.768-khz clock pulses. the supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2.1 or 1.35v. each function has a monitor bit. i.e. the po n bit is for the power-on reset circuit, and xst bit is for the oscillation halt sensing circuit, and vdet is for the suppl y voltage monitoring circuit. pon and vdet bits are activated to ?h?. however, xst bit is activated to ?l?. the pon and vdet accept only the writing of 0, but xst accepts the writing of 0 and 1. the pon bit is set to 1, when vdd power-up from 0v, but vdet is set to 0, and xst is indefinite. the functions of these three monitor bits are shown in the table below. pon x st vdet function monitoring for the power-on reset function monitoring for the oscillation halt sensing function a drop in supply voltage below a threshold voltage of 2.1 or 1.35v address d4 in address fh d5 in address fh d6 in address fh activated high low high when vdd power up from 0v 1 indefinite 0 accept the writing 0 only both 0 and 1 0 only the relationship between the pon, xst , and vdet is shown in the table below. pon xst vdet conditions of supply voltage and oscillation condition of oscillator, and back-up status 0 0 0 halt on oscillation, but no drop in vdd supply voltage below threshold voltage halt on oscillation cause of condensation etc. 0 0 1 halt on oscillation and drop in vdd supply voltage below threshold voltage, but no drop to 0v halt on oscillation cause of drop in back-up battery voltage 0 1 0 no drop in vdd supply voltage below threshold voltage and no halt in oscillation normal condition 0 1 1 drop in vdd supply voltage below threshold voltage and no halt on oscillation no halt on oscillation, but drop in back-up battery voltage 1 * * drop in supply voltage to 0v power-up from 0v,
r2061 series 39 32768hz oscillation power-on reset flag (pon) oscillation halt sensin g fla g ( xst ) threshold voltage (2.1v or 1.35v) vdd vdd supply voltage monitor flag (vdet) internal initialization period (1 to 2 sec.) vdet 0 xst 1 pon 0 vdet 0 xst 1 pon 1 vdet 0 xst 1 pon 0 internal initialization period (1 to 2 sec.) when the pon bit is set to 1 in the control register 2, the dev, f6 to f0, wale, dale, 12 /24, scratch2, test, ct2, ct1, ct0, vdsl, vdet, scratch1, ctfg, wafg, and dafg bits are reset to 0 in the oscillation adjustment register, the control register 1, and the control register 2. the pon bit is also set to 1 at power-on from 0 volts. < considerations in using osc illation halt sensing circuit > be sure to prevent the oscillation halt sensing circuit from malfuncti oning by preventing the following: 1) instantaneous power-down on the vdd 2) condensation on the quartz crystal unit 3) on-board noise to the quartz crystal unit 4) applying to individual pins voltage exceeding their respective maximum ratings in particular, note that the xst bit may fail to be set to 0 in the presence of any applied supply voltage as illustrated below in such events as back up battery installation. further, give special considerations to prevent excessive chattering in the oscillation halt sensing circuit. vdd
r2061 series 40 ? voltage monitoring circuit r2061 incorporates two kinds of voltage monitoring function. these are shown in the table below. vcc voltage monitoring circuit vcc voltage monitoring circuit (vdet) purpose cpu reset output back-up battery checker monitoring supply voltage vcc pin vdd pin (supply voltage for the internal rtc circuit) output for result vdcc pin store in the control register 2 (d6 in address fh) function after falling vcc, vdcc outputs ?l?. t dealy after rising vcc, vdcc outputs ?h? (off) below the threshold voltage, sw1 turns off and sw2 turns on. over the threshold voltage, sw1 turns on and sw2 turns off. detector threshold (falling edge of power supply voltage) -v det1 selecting from v deth or v detl by writing to the register (d7 in address fh) detector released voltage (rising edge of power supply voltage) +v det1 same as falling edge ( no hysteresis) the way to monitor always one time every second the vdd supply voltage monitoring circuit is configured to conduct a sampling operation during an interval of 7.8ms per second to check for a drop in supply voltage bel ow a threshold voltage of 2.1 or 1.35v for the vdsl bit setting of 0 (the default setting) or 1, respectively, in t he control register 2, thus minimizing supply current requirements as illustrated in the timing chart below. this circuit suspends a sampling operation once the vdet bit is set to 1 in the control register 2. t he vdd supply voltage monitor is useful for back-up battery checking. vdet ( d6 in address fh ) pon vdd 2.1v or 1.35v 1s vdet 0 7.8ms sampling timing for vdd supply voltage monitor internal initialization period ( 1 to 2sec. ) pon 0 vdet 0
r2061 series 41 the vcc supply voltage monitor circuit operates always. when vcc rising over +v det1 , sw1 turns on, and sw2 turns off. and t delay after rising vcc, vdcc outputs off(h). but when oscillation is halt, vcc outputs off(h) t delay after oscillation starting. when vcc falling beyond -v det1 , sw1 turns off, and sw2 turns on. and vdcc outputs ?l?. vdd 32768hz oscillation vdcc +v det1 vcc sw1 sw2 t delay t delay t delay on on on on on same voltage level as vsb oscillation starting -v det1 battery switch over circuit r2061 incorporates thr ee power supply pins, vdd, vcc, and vsb. vdd pin is the power supply pin for internal real time clock circuit. when vcc voltage is lower than v det1 , vsb supplies the power to vdd, and when higher than v det1 , vcc supplies the power to vdd. the ti ming chart for vcc, vdd, and vsb is shown following. vdd +v det1 vcc vsb ( 1 ) ( 2 ) ( 3 ) ( 3 ) ( 2 ) -v det1 (1) when vsb is 0v and vcc is rising from 0v, vdd follows half of vcc voltage level. after vcc rising over +v det1 , vdd follows vcc voltage level. (2) when vcc is higher than +v det1 , vdd level is equal to vcc. (3) after vcc falling beyond ?v det1, vdd level is equal to vsb.
r2061 series 42 alarm and periodic interrupt the r2061 incorporates the alarm interrupt circuit and t he periodic interrupt circuit that are configured to generate alarm signals and periodic interrupt signals for output from the intr pin as described below. (1) alarm interrupt circuit the alarm interrupt circuit is configured to generate alarm signals for output from the intr , which is driven low (enabled) upon the occurrence of a match between curren t time read by the time counters (the day-of-week, hour, and minute counters) and alarm time preset by the alarm registers (the alarm_w registers intended for the day-of-week, hour, and minute digit settings and the alar m_d registers intended for the hour and minute digit settings). (2) periodic interrupt circuit the periodic interrupt circuit is configured to generate eit her clock pulses in the pulse mode or interrupt signals in the level mode for output from the intr pin depending on the ct2, ct1, and ct0 bit settings in the control register 1. the above two types of interrupt signals are monitored by the flag bits (i.e. the wafg, dafg, and ctfg bits in the control register 2) and enabled or disabled by t he enable bits (i.e. the wale, dale, ct2, ct1, and ct0 bits in the control register 1) as listed in the table below. flag bits enable bits alarm_w wafg (d1 at address fh) wale (d7 at address eh) alarm_d dafg (d0 at address fh) dale (d6 at address eh) peridic interrupt ctfg (d2 at address fh) ct2=ct1=ct0=0 (these bit setting of ?0? disable the periodic interrupt) (d2 to d0 at address eh) * at power-on, when the wale, dale, ct2, ct1, and ct0 bits are set to 0 in the control register 1, the intr pin is driven high (disabled). * when two types of interrupt sign als are output simultaneously from the intr pin, the output from the intr pin becomes an or waveform of their negative logic. example: combined output to intr pin under control of alarm_d and periodic interrupt periodic interrupt intr alarm_d in this event, which type of inte rrupt signal is output from the intr pin can be confirmed by reading the dafg, and ctfg bit settings in the control register 2.
r2061 series 43 ? alarm interrupt the alarm interrupt circuit is controlled by the enable bits (i.e. the wale and dale bits in the control register 1) and the flag bits (i.e. the wafg and dafg bits in the control register 2). the enable bits can be used to enable this circuit when set to 1 and to disable it when set to 0. when intended for reading, the flag bits can be used to monitor alarm interrupt signals. when intended fo r writing, the flag bits will cause no event when set to 1 and will drive high (disable) the alarm interrupt circuit when set to 0. the enable bits will not be affected even when the flag bits ar e set to 0. in this event, therefore, the alarm interrupt circuit will continue to func tion until it is driven low (enabled ) upon the next occu rrence of a match between current time and preset alarm time. the alarm function can be set by presetting desired alarm time in the alarm registers (the alarm_w registers for the day-of-week digit settings and both the alarm_w registers and the al arm_d registers for the hour and minute digit settings) with the wale and dale bits once se t to 0 and then to 1 in the control register 1. note that the wale and dale bits should be once set to 0 in order to disable the alarm interrupt circuit upon the coincidental occurrence of a match between current ti me and preset alarm time in the process of setting the alarm function. current time = preset alarm time wale 1 (dale) interval (1min.) during which a match between current time and preset alarm time occurs current time = preset alarm time wafg 1 (dale) current time = preset alarm time wale 0 (dale) current time = preset alarm time intr after setting wale(dalw) to 0, alarm registers is set to current time, and wale(dale) is set to 1, intr will be not driven to ?l? immediately, intr will be driven to ?l? at next alarm setting time.
r2061 series 44 ? periodic interrupt setting of the periodic selection bits (ct2 to ct0) enables periodic interrupt to the cpu. there are two waveform modes: pulse mode and level mode. in the pulse mode, the output has a waveform duty cycle of around 50%. in the level mode, the output is cyclically driven low and, when the ctfg bit is set to 0, the output is return to high (off). description ct2 ct1 ct0 wave form mode interrupt cycle and falling timing 0 0 0 - off(h) (default) 0 0 1 - fixed at ?l? 0 1 0 pulse mode *1) 2hz(duty50%) 0 1 1 pulse mode *1) 1hz(duty50%) 1 0 0 level mode *2) once per 1 second (synchronized with second counter increment) 1 0 1 level mode *2) once per 1 minute (at 00 seconds of every minute) 1 1 0 level mode *2) once per hour (at 00 minutes and 00 seconds of every hour) 1 1 1 level mode *2) once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month) *1) pulse mode: 2-hz and 1-hz clock pulses are output in synchronizat ion with the increment of the second counter as illustrated in the timing chart below. intr pin rewriting of the second counter ctfg bit a pprox. 92 s (increment of second counter) in the pulse mode, the increment of the second counter is delayed by approximately 92 s from the falling edge of clock pulses. consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. rewriting the second counter will reset the other time counters of less than 1 second, driving the intr pin low. *2) level mode: periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. the increment of the second counter is synchronized with the falling edge of periodic interrupt signals. for example, periodic interrupt signals with an in terrupt cycle setting of 1 second are output in synchronization with the increment of the se cond counter as illustrated in the timing chart below.
r2061 series 45 intr pin (increment of second counter) ctfg bit setting ctfg bit to 0 setting ctfg bit to 0 (increment of second counter) (increment of second counter) *1), *2) when the oscillation adjustment circuit is used, the interrupt cycl e will fluctuate once per 20sec. as follows: pulse mode: the ?l? period of output pulses w ill increment or decrement by a maximum of 3.784ms. for example, 1-hz clock pulses will have a duty cycle of 50 0.3784%. level mode: a periodic interrupt cycle of 1 second will increment or decrement by a maximum of 3.784ms.
r2061 series 46 typical applications ? typical power circuit configurations vdd vsb vcc vss 0.1 f cpu power supply the case of back-up b y primary battery cr2025 etc. vsb vd d vc c vss 0.1 f cpu power supply ml614 etc. the case of back-up by capacitor or secondary battery (charging voltage is equal to cpu power supply voltage) vsb vd d vc c vss 0.1 f cpu power supply (3v) 5v double layer capacitor etc. the case of back-up by capacitor or secondary battery (charging voltage is not equal to cpu power supply voltage) vdd pin cannot be connected to any additional heavy l oad components such as sram. and vdd pin must be connected c2, and c2 should be over 0.1 f. vdd cpu power supply vcc vsb c3 voltage detector sw1 sw2 c2 r1 cpu vbat -v det1 rcpu r2061 series when secondary battery or double layer capacitor connects to vdd pin, after cpu power supply turning off, secondary battery discharges through the root above figure. if r1 is much smaller than cpu impedance (rcpu), vcc voltage keeps higher than -v det1 , and sw1 keeps on. therefore r1 must be specified by following formula. r1 > rcpu x (vbat - (-v det1 )) / (-v det1 ) r1 is specified by back-up battery or double layer capa citor, too. please check the data sheet for back-up devices.
r2061 series 47 ? connection of cin pin please connect capacitor over 0.1 f between cin and vss pin. ? connection of intr and vdcc pin the intr and vdcc pins follow the n-channel open drain output logic and contains no protective diode on the power supply side. as such, it can be connected to a pull-up resistor of up to 5. 5 volts regardless of supply voltage. vsb oscin oscout intr or vdcc *1) 32768hz b a backup power supply cpu power supply vss *1) depending on whether the intr and vdcc pins are to be used during battery backup, it should be connected to a pull-up resistor at the following different positions: (1) position a in the left diagram when it is not to be used during battery backup. (2) position b in the left diagram when it is to be used during battery backup.
r2061 series 48 typical characteristics ? time keeping current (i sb ) vs. supply voltage (v sb ) (topt=25 c) test circuit 0 0.1 0.2 0.3 0.4 0.5 0123456 v sb (v) time keeping current (ua) vcc vsb vdd cin vss oscin oscout intr vdcc ce sclk sio 0.1 f 0.1 f a ? stand-by current (i cc ) vs. supply voltage (v cc ) (topt=25 c) test circuit 0 0.5 1 1.5 2 0123456 v cc (v) stand-by current (ua) vcc vsb vdd cin vss oscin oscout ce sclk sio 0.1 f 0.1 f a intr vdcc ? time keeping current (isb) vs. operating temperature (topt) (v sb =3v) test circuit 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 -50 -25 0 25 50 75 100 operating temperature (celsius) time keeping current (ua) vcc vsb vdd cin vss oscin oscout ce sclk sio 0.1 f 0.1 f a intr vdcc
r2061 series 49 ? stand-by current (i cc ) vs. operating temperature (topt) (v cc =3v) test circuit 0 0.5 1 1.5 2 -50 -25 0 25 50 75 100 operating temperature (celsius) stand-by current(ua) vcc vsb vdd cin vss oscin oscout ce sclk sio 0.1 f 0.1 f a intr vdcc ? cpu access current vs. sclk clock frequency (khz) (topt=25 c) 0 20 40 60 80 0 200 400 600 800 1000 scl clock frequency (khz) cpu access current (ua) ? oscillation frequency deviation ( ? f/f0) vs. operating temperature (topt) (v cc =3v topt=25 c as standard) test circuit -160 -140 -120 -100 -80 -60 -40 -20 0 20 -50 -25 0 25 50 75 100 operating temperature topt(celsius) oscillation frequency deviation df/f0(ppm) vcc vsb vdd cin vss oscin oscout ce sclk sio 0.1 f 0.1 f frequency counter intr vdcc v cc =5v v cc =3v
r2061 series 50 ? frequency deviation ( ? f/f0) vs. supply voltage (v sb /v cc ) (topt=25 c) v cc /v sb =3v as standard test circuit -4 -3 -2 -1 0 1 2 0123456 vcc/vsb(v) frequency deviation df/f0(ppm) vcc vsb vdd cin vss oscin oscout ce sclk sio 0.1 f 0.1 f frequency counter intr vdcc ? frequency deviation ( ? f/f0) vs. cgout (topt=25 c, v cc =3v)cgout=0pf as standard test circuit -40 -30 -20 -10 0 10 0 5 10 15 20 cgout(pf) frequency deviation df/f0(ppm) vcc vsb vdd cin vss oscin oscout ce sclk sio 0.1 f 0.1 f frequency counter intr vdcc ? detector threshold voltage (+v det1 /-v det1 ) vs. operating temperature (topt) (r2061k01) (v sb =3v) test circuit 1.6 1.7 1.8 1.9 -50 -25 0 25 50 75 100 operating temperature topt(celsius) detector threshold voltage vdet1(v) vcc vsb vdd cin vss oscin oscout ce sclk sio 0.1 f 0.1 f intr vdcc +v det1 -v det1
r2061 series 51 ? vcc-vdd(v ddout1 ) vs. output load current (i out1 ) (topt=25 c) test circuit -0.5 -0.4 -0.3 -0.2 -0.1 0 0246810 output load current iout1(ma) vcc-vdd(v) vcc vsb vdd cin vss oscin oscout ce sclk sio 0.1 f 0.1 f a intr vdcc ? vsb-vdd(v ddout2 ) vs. output load current (i out2 ) (topt=25 c) test circuit -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 00.511.522.53 output load current iout2(ma) vsb-vdd(v) vcc vsb vdd cin vss oscin oscout ce sclk sio 0.1 f 0.1 f a intr vdcc ? v ol vs. i ol ( vdcc pin) ? v ol vs. i ol ( intr pin) (topt=25 c, v sb =v cc =1.5v) (topt=25 c) 0 0.1 0.2 0.3 0.4 012345 i ol (ma) v ol (v) 0 0.1 0.2 0.3 0.4 0246810 i ol (ma) v ol (v) v cc =3v v cc =5v v sb =3v v sb =2v v sb =1v v cc =5v v cc =3v v cc =2.5v v cc =2.0v
r2061 series 52 typical software-based operations ? initialization at power-on start *1) yes no vdet=0? warning back-up batter y run-down set oscillation adjustment register and control register 1 and 2, etc. power-on *2) *4) *3) pon=1? yes no *1) after power-on from 0 volt, the process of internal initialization require a time span on 1sec, so that access should be done after vdcc turning to off(h). *2) the pon bit setting of 0 in the control register 1 indicates power-on from backup battery and not from 0v. for further details, see "p.38 power-on re set, oscillation halt sensing, and supply voltage monitoring ? pon, xst , and vdet ". *3) this step is not required when the suppl y voltage monitoring circuit is not used. *4) this step involves ordinary initialization including the oscillation adjustment register and interrupt cycle settings, etc. ? writing of time and calendar data write to time counter and calendar counter *2) ce l *3) ce h *1) *1) when writing to clock and calendar counters, do not insert ce=l until all times from second to year have been written to prevent error in writing time. (detailed in "p.24 ? considerations in reading and writing time data under special condition". *2) any writing to the second counter will reset divider units lower than the second digits. the r2061 may also be initialized not at power-on but in the process of writing time and calendar data.
r2061 series 53 ? reading time and calendar data (1) ordinary process of reading time and calendar data read from time counter and calendar counter *1) ce l ce h *1) (2) basic process of reading time and calendar data with periodic interrupt function *2) other interrupt processes set periodic interrupt cycle selection bits ctfg=1? read from time counter and calendar counter yes no control register 2 (x1x1x011) generate interrupt in cpu *1) *3) *1) this step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) this step must be completed within 0.5 second. *3) this step is intended to set the ctfg bit to 0 in the control register 2 to cancel an interrupt to the cpu. *1) when reading to clock and calendar counters, do not insert ce=l until all times from second to year have been read to prevent error in reading time. (detailed in "p.24 ? considerations in reading and writing time data under special condition".
r2061 series 54 (3) applied process of reading time and calendar data with periodic interrupt function time data need not be read from all the time counters when used for such ordinary purposes as time count indication. this applied process can be used to read time and calendar data with substantial reductions in the load involved in such reading. for time indication in "day-of-month, day-of -week, hour, minute, and second" format: *2) other interrupts processes control register 1 (xxxx 0100) control register 2 (x1x1x011) sec.=00? yes no use previous min.,hr., day,and day-of-week data generate interrupt to cpu *1) *3) ctfg=1? control register 2 (x1x1x011) yes read min.,hr.,day, and day-of-week *4) no *1) this step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) this step must be completed within 0.5 sec. *3) this step is intended to read time data from all the time counters only in the first session of reading time data after writing time data. *4) this step is intended to set the ctfg bit to 0 in the control register 2 to cancel an interrupt to the cpu.
r2061 series 55 ? interrupt process (1) periodic interrupt *2) other interrupt processes set periodic interrupt cycle selection bits ctfg=1? conduct periodic interru p t yes no control register 2 (x1x1x011) generate interrupt to cpu *1) *1) this step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) this step is intended to set the ctfg bit to 0 in the control register 2 to cancel an interrupt to the cpu.
r2061 series 56 (2) alarm interrupt *3) other interrupt processes set alarm min., hr., and day-of-week registers wafg or dafg=1? conduct alarm interrupt yes no control register 2 (x1x1x101) generate interrupt to cpu *1) wale or dale 0 *2) wale or dale 1 *1) this step is intended to once disable the alarm interrupt circuit by setting the wale or dale bits to 0 in anticipation of the coincidental occurrence of a match between curr ent time and preset alarm time in the process of setting the alarm interrupt function. *2) this step is intended to enable the alarm interrupt function after completion of all alarm interrupt settings. *3) this step is intended to once cancel the alarm interrupt function by writing the settings of "x,1,x, 1,x,1,0,1" and "x,1,x,1,x,1,1,0" to the alarm_w registers and t he alarm_d registers, respectively.

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